Design and FPGA Implementation of LDPC Decoder using High Level Modeling for WSNs
Mallesha B. Y
Mallesha B. Y, P G Student, Visvesvaraya Technological University Extension Centre, UTL Technologies Ltd., Yeshwantpur, Bangalore, India.
Manuscript Received on September 10, 2015. | Revised Manuscript Received on September 19, 2015. | Manuscript published on September 20, 2015. | PP: 4-6 | Volume-3 Issue-10, September 2015. | Retrieval Number: J06660931015/2015©BEIESP
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Abstract: Low density parity check (LDPC) codes are error correcting codes that offer huge advantages in terms of coding gain, throughput and power dissipation in digital communication systems. Error correction algorithms are often implemented in hardware for fast processing to meet the real-time needs of communication systems. However, traditional hardware implementation of LDPC decoders require large amount of resources, rendering them unsuitable for use in energy constrained sensor nodes of wireless sensor networks (WSN). This paper investigates the use of short-length LDPC codes for error correction in WSN. It presents the LDPC decoder designs, implementation, resource requirement and power consumption to judge their suitability for use in the sensor nodes of WSN. Due to the complex interconnections among the variable and check nodes of LDPC decoders, it is very time consuming to use traditional hardware description language (HDL) based approach to design these decoders. This paper presents an efficient automated high-level approach to designing LDPC decoders using a collection of high-level modeling tools. The automated high-level design methodology provides a complete design flow to quickly and automatically generate, test and investigate the optimum (length) LDPC codes for wireless sensor networks to satisfy the energy constraints while providing acceptable bit-error-rate performance.
Keywords: Error Correction Coding; Wireless Communication; Wireless Sensor Networks; Digital System;