Design of Fault Tolerant Memory System with Difference Set Cyclic Codes
Swarnalatha Eluri1, Hemalatha Rallapalli2

1Swarnalatha Eluri, Assistant Professor, Department of ECE, Jawaharlal Nehru Institute of Technology, Hyderabad.
2Hemalatha Rallapalli, Assistant Professor, Department of ECE, University College of Engineering, Osmania University, Hyderabad.
Manuscript received on October 05, 2013. | Revised Manuscript Received on October 16, 2013. | Manuscript published on October 20, 2013. | PP: 67-71 | Volume-1, Issue-11, October 2013. | Retrieval Number: J03140911013/2013©BEIESP
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Abstract: The problem of single event upset (SEU) due to higher integration, smaller dimensions and lower voltages is very common and need to be addressed. The effect of SEU is not only present at the terrestrial environments but also at the ground level. The SEUs also result in silent data corruption which results in the further corruption of data, especially in memories. A special class of LDPC codes called Difference Set Cyclic Codes (DSCC) is used to design a fault tolerant memory system that detects the silent data corruption. The DSCC is simple and easy to implement.
Keywords: Difference Set Cyclic Codes (DSCC), LDPC, Majority Logic Fault Detector (MLDD), Single Event Upsets (SEU).