Abstract: Here we aim to build a model of the multi load material supply system which is the hybrid of AGV (Automated guided vehicle) and AS/RS (Automated storage/Retrieval system) system. The AGV base provides movement in the manufacturing facility and AS/RS provides storage of the material. The machine can be designed depending on the AGV load caring capacity and variety of material need to be carried. Depending upon number of variety of products and requirements, compartment can be increased or decreased. One of major advantage of this kind of machine in normal AGV is it has high throughput. Since single machine can carry more products hence number of AGVs needed to handle material is less thereby traffic in the manufacturing environment can be decreased and more efficiency in material handling transportation can be achieved. Due to decrease in AGV numbers in manufacturing environment, cost of handling and maintenance them is reduced hence it saves money and increase efficiency.
Keywords: Multi-load Robots, Multi Load AGVs, Revolutionary AGV Design.
1. D. VenkataRamanaiah, Ashok B, “Performance Of Multi-Load Agv Systems Under Different Guide Path Configurations,”International Journal of Technology and Engineering Sciences Vol.1 (1), ISSN: 2320-8007, 2012.
2. Ryunosuke Takano, Toshimitsu Higashi, Hirofumi Tamura, Mingang Cheng, and Jun Ota, “Mixed-load Transportation Scheduling in a Floor Warehouse Environment,” 2008 IEEE/RSJ International Conference on Intelligent Robots and Systems Acropolis Convention Center Nice, France, Sept, 22-26, 2008.
3. Parham Azimi, HasanHaleh, andMehranAlidoost, “The Selection of the Best Control Rule for a Multiple-Load AGV System Using Simulation and Fuzzy MADM in a Flexible Manufacturing System,” Hindawi Publishing Corporation Modelling and Simulation in Engineering Volume 2010, Article ID 821701, 11 pagesdoi:10.1155/2010/821701.
4. SajjadYaghoubi, SanamKhalili, Reza Mohammad Nezhad, Mohammad Reza Kazemi&MahsaSakhaiifar,“Designing And Methodology Of Automated Guided Vehicle Robots/ Self-Guided Vehiclesystems, Future Trends”, www.arpapress.com/Volumes/Vl13Issue1/IJRRAS_13_1_30,IJRRAS October 2012.
5. ZhengYao,Grad. Sch. of Inf., Production & Syst., Waseda Univ., Kitakyushu, Japan, Fujimura, S. Computer Science and Information Technology (ICCSIT), 2010 3rd IEEE International Conference on Volume: 2 Date of Conference: 9-11 July 2010, Page(s) 255 – 259, Print ISBN: 978-1-4244-5537-9.
Abstract: This paper reviews a method for a robot can locate and track landmarks using segmentation algorithm within proper distance, It extracts text or sign from the landmark and inputs them into the OCR engine for recognition. Simultaneously, a projection analysis of texts or signs of the landmark is conducted, finally by identifying the semanteme of text or signs the robot can find the routes to the destinations automatically. Experiments on the robot model shows that this method can be used to accomplish maples navigation task perfectly in the indoors or customised environment. Being able to navigate with landmarks in real life directly without generating maps or resetting new navigation sign for robots. Specially, this method can be applied in the field of service robots rapidly, which can enhance their adaptability and viability significantly.
Keywords: Mapless navigation, Landmark recognition, OCR, Kohonen Neural Network.
1. R.C. Gonzalez and R.E. Woods, Digital Image Processing, second edition, Pearson Education, 2005
2. F. Moutarde, A. Bargeton, A. Herbin, and L. Chanussot, “Robust on vehicle real-time visual detection of American and European speed limit signs, with a modular traffic sign recognition system,” in Intelligent Vehicles Symposium, IEEE 2007 .
3. C. Keller, C. Sprunk, C. Bahlmann, J. Giebel, and G. Baratoff, “Real-time recognition of us speed signs,” in Intelligent Vehicles Symposium, IEEE 2008 .
4. G. Qingji, Y. Yue, and Y. Guoqing, “Detection of public information sign in airport terminal based on multi-scales spatio-temporal vision information,” International Conference on IEEE 2008.
5. J. Maye, L. Spinello, R. Triebel, and R. Siegwart, “Inferring the semantics of direction signs in public places,” in Robotics and Automation (ICRA), IEEE 2010.
6. T. Breuer, G. Giorgana Macedo, R. Hartanto, N. Hochgeschwender, D. Holz, F. Hegger, Z. Jin and G. Kraetzschmar “Johnny: An autonomous service robot for domestic environments,” Journal of Intelligent & Robotic Systems, Jul. 2011.
7. I. Posner, P. Corke, and P. Newman, “Using text-spotting to query the world,” in Intelligent Robots and Systems (IROS), 2010 IEEE/RSJ International Conference on IEEE 2010.
8. Auranuch Lorsakul , Jackrit Suthakorn “Traffic Sign Recognition for Intelligent Vehicle/Driver Assistance System Using Neural Network on OpenCV”. International Conference on Ubiquitous Robots and Ambient Intelligence (URAI 2007).
9. J. Heaton, Introduction to Neural Network in Java, HR publication, 2010.
10. N. Otsu, “A Threshold Selection Method from Gray-Level Histograms”, IEEE Transactions on Systems, Man, and Cybernetics, 2001.
11. A.K. Jain and T. Taxt, Feature Extraction Methods for Character Recognition - a survey, Michigan State University, 2001.
12. Adnan Md. Shoeb Shatil, “Research Report on Bangla Optical Character Recognition Using Kohonen Network”, BRAC University, 2005.
Abstract: Asynchronous serial communication is usually implemented by Universal Asynchronous Receiver Transmitter (UART), mostly used for short distance, low speed, low cost data exchange between processor and peripherals. UART allows full duplex serial communication link, and is used in data communication and control system. There is a need for realizing the UART function in a single or a very few chips. Further, design systems without full testability are open to the increased possibility of product failures and missed market opportunities. Also, there is a need to ensure the data transfer is error proof. This paper targets the introduction of Built-in self test (BIST) and Status register to UART, to overcome the above two constraints of testability and data integrity. The 8-bit UART with status register and BIST module is coded in Verilog HDL and synthesized and simulated using Xilinx XST and ISim version 14.4 and realized on FPGA. The results indicate that this model eliminates the need for higher end, expensive testers and thereby it can reduce the development time and cost.
Keywords: UART, BIST, Error check, Status register, LFSR.
1. Naresh, Vatsalkumar and Vikaskumar Patel, “VHDL Implementation of UART with Status Register”, in the proceedings of International Conference on Communication Systems and Network Technologies, IEEE Computer Society, 11-13th May 2012, DOI: 10.1109/CSNT.2012.164, pp.750-754.
2. Fang Yi-yuan and Chen Xue-jun, “Design and Simulation of UART Serial Communication Module Based on VHDL”, in the proceedings of 3rd International Workshop on Intelligent Systems and Applications (ISA), IEEE, May 2011, DOI: 10.1109/ISA.2011.5873448, pp.1-4.
3. Mohd Yamani Idna Idris, Mashkuri Yaacob and Zaidi Razak, “A VHDL Implementation of UART Design with BIST Capability”, in the proceedings of Malaysian Journal of Computer Science, June 2006, Vol. 19(1), pp. 73-86.
4. Dr. Garima Bandhawarkar Wakhle, Iti Aggarwal and Shweta Gaba, “Synthesis and Implementation of UART using VHDL Codes”, in the proceedings of International Symposium on Computer, Consumer and Control, IEEE June 2012, DOI: 10.1109/IS3C.2012.10.
5. Norhuzaimin J and Maimun H.H, “The design of high speed UART”, in the proceedings of Asia-Pacific Conference on Applied Electromagnetics, APACE 05, IEEE, 20-21st Dec. 2005, DOI: 10.1109/APACE.2005.1607831, pp.5-8.
6. Dr. T.V.S.P.Gupta, Y. Kumari and M. Ashok Kumar, “UART realization with BIST architecture using VHDL”, in the proceedings of International Journal of Engineering Research and Applications, February 2013, Vol. 3, Issue 1, ISSN: 2248-9622, pp.636-640.
7. Shikha Kakar, Balwinder Singh and Arun Khosla, “Implementation of BIST Capability using LFSR Techniques in UART”, in the proceedings of International Journal of Recent Trends in Engineering, May 2009, Vol 1, No. 3.
8. Sybille Hellebrand, Birgit Reeb and Steffen Tarnick, “Pattern Generation for a Deterministic BIST Scheme”, in the proceedings of IEEE/ACM International Conference on Computer-Aided Design, ICCAD-95, Digest of Technical Papers, November 1995, DOI: 10.1109/ICCAD.1995.479997, pp. 88-94.
9. Mahat N.F, “Design of a 9-bit UART module based on Verilog HDL”, in the proceedings of 10th IEEE International Conference on Semiconductor Electronics (ICSE), 19-21st Sept. 2012, DOI: 10.1109/SMElec.2012.6417210, pp. 570-573.