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Volume-1 Issue-5: Published on April 20, 2013
Volume-1 Issue-5: Published on April 20, 2013

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Volume-1 Issue-5, April 2013, ISSN: 2319-9598 (Online)
Published By: Blue Eyes Intelligence Engineering & Sciences Publication Pvt. Ltd. 

Page No.



Nagesh M. Kulkarni, D. G. Gaidhankar

Paper Title:

Analysis and Design of Ferrocement Panels an Experimental Study

Abstract: Ferrocement is a form of reinforced concrete that differs from conventional reinforced or prestressed concrete primarily by the manner in which the reinforcing elements are dispersed and arranged. It consists of closely spaced, multiple layers of mesh or fine rods completely embedded in cement mortar. This paper describes the various experiments conducted on ferrocement panels in literature review and the conclusions and remarks drawn by the authors. The results obtained are going to help in the project work to investigate the behavior of ferrocement panels for various parameters and loading. This is useful to find solutions by searching new design techniques and method of constructions.

Cement mortar, Ferrocement, Mesh, Panels.


1.        Ferrocement floor and roof system for buildings By  Dr.T.S.Thandavamoorty Adhiparasakti Engineering college Melmaaruvathur
2.        Flexural Behavior of Flat and Folded Ferrocement Panels by Mohamad Mahmood Civil Engineering department Mosul University Iraq

3.        Structural behavior of ferrocement system for roofing  By Wail N. Al-Rifaie University of Nottingham

4.        Research Needs in Ferrocement Technology by Dr.P.N.Divekar, President, Ferrocement society, Pune

5.        Effect Of Wire Mesh Orientation On Ferrocement element by Dr. S.K. Kaushik Professor and Head, Department of Civil Engineering, Indian Institute of Technology, Roorkee

6.        Performance of Precast Ferrocement Panel for Composite Masonry Slab System by Y. Yardim, Universiti Putra Malaysia

7.        Applications of Ferrocement in Strengthening of Unreinforced Masonry Columns By Abid A. Shah

8.        Utilization of Ferrocement as Flexural Building Member (Applied as a Hollow Box Joist)By R Abasolo, C Bandivs, Civil Engineering department College of Engineering Xavier University-Philippines

9.        Design of College Building with Ferrocement Element By Arun Purandare,  Structural Consultant, Pune

10.     ACI Committee 549, “State-of-the-art report on ferrocement”, ACI549-R97, in Manual of Concrete Practice, ACI, Detroit, 1997, 26 pp

11.     ACI committee 549-1R-88, “Guide for design construction and repair of ferrocement,” ACI 549-1R-88 and 1R-93, in Manual of Concrete Practice, ACI, Detroit, 1993, 27 pp.

12.     Association of Structural Engineers of the Philippines,Inc. (2001). National structural code of the Philippines (NSCP) 2001, Volume1.Structural Concrete. Philippines.




S. Harippriya, T. Kalaikumaran, S. Karthik

Paper Title:

Secure Clustering in a Distributed Network

Abstract: Data Mining plays a major role in storage of vast quantities of data. It extracts valuable knowledge, which helps organizations to obtain better results by pooling their data together. Distributed data mining is concerned about data that are shared among multiple organizations. A complementary approach to privacy-preserving data mining uses randomization techniques. Privacy-preserving data mining solutions have been presented both with respect to horizontally and vertically portioned databases, in which earlier data objects with the same attributes for the same data objects are owned by each party, respectively. The quality of a set of clusters can be measured using the value of an objective function which is taken to be the sum of the squares of the distances of each point from the centre of the cluster to which it is assigned.

Arbitrarily partitioned Data, Data Mining.


1.        Agrawal.R and Srikant.R(2000)’Privacy preserving data mining’,In Proc.ACM SIGMID Conf. on Management of Data,pages 439-450.ACM Press
2.        Ali Inan, Yucel Saygin, Erkay Savas, Ayca Azg─▒n Hintoglu, Albert Levi,2006. ‘Privacy Preserving Clustering on Horizontally Partitioned Data’, Proceedings of the 22nd International Conference on Data Engineering Workshops (ICDEW'06)

3.        Chris Clifton,(2001)‘Privacy Preserving Distributed Data Mining’

4.        Geetha Jagannathan, Krishnan Pillaipakkamnatt and Rebecca N. Wright,’A New Privacy-Preserving Distributed k-Clustering Algorithm’

5.        Goethals.B,Laur.S,Lipmaa.H, and Mielikainen.T,(2004)’On Secure scalar product computation for privacy-preserving data mining’.In The 7th Annual International Conf. in Information Security and Cryptology

6.        Golreich.O(2004)’Foundations of Cryptography’,Vol II Cambridge University Press

7.        Krishna Prasad.P and Pandu Rangan.C(2007) ’Privacy Preserving BIRCH Algorithm for Clustering over Arbitrarily Partitioned Databases’ R. Alhajj et al. (Eds.): ADMA 2007, LNAI 4632, pp. 146–157, 2007. © Springer-Verlag Berlin Heidelberg

8.        Lindell.Y and Pinkas.B(2000)’Privacy preserving data mining’,Lecture Notes in Computer Science,1880

9.        Lloyd.S.P(1982)’Least squares quantization in PCM’,IEEE Transactions on Information Theory,28:129-137

10.     MacQueen.J,(1967)’Some methods for classification and analysis of multivariate observations’.In Proc.Fifth Berkeley Symposium on Mathematical Statistics and probability,volume 1,pages 2          81-296

11.     Maneesh Upmanyu, Anoop M. Namboodiri, Kannan Srinathan, and C.V. Jawahar(2010)’Efficient Privacy Preserving K-Means Clustering’, H. Chen et al. (Eds.): PAISI 2010, LNCS 6122, pp. 154–166. © Springer-Verlag Berlin Heidelberg

12.     Oliveria.S and Zaiane.O.R(2003)’Privacy preserving clustering by data transformation’ In Proc.18th Brazilian Symposium on Databases, pages 304-318

13.     Prakash.V.S,Shanmugam.A,Murugesan.P (2012) ‘Efficient Cluster Based Privacy Preservation Data Perturbation Technique in Multi-Partitioned Datasets’,European Journal of Scientific Research, ISSN 1450-216X Vol. 86 No 2 September, 2012, pp.254-263

14.     Shuguo HAN, and Wee Keong NG(2007)’Multi-Party Privacy-Preserving Decision Trees for Arbitrarily Partitioned Data’ International Journal Of Intelligent Control And Systems Vol. 12, No. 4, 351-358

15.     Vaidya.J and Clifton.C(2003)’Privacy preserving k-means clustering over vertically partitioned data’ In Proc. 9th ACM SIGKDD International Conf. on Knowledge Discovery and Data Mining.ACM Press.




Mukesh Kumar Thakur, Ravi Shankar Kumar, Mohit Kumar, Raju Kumar

Paper Title:

Wireless Fingerprint Based Security System Using Zigbee Technology

Abstract: Among the huge requirements, the one and only one requirement which has a vital importance in our daily life is “Security”. It may be for application, information, data, network, home, financial, and national security like parliament etc. In this present day we have already several type of security system like CCTV,  barcode, identity card etc. which is based on the various type of technology and has tedious processing, which is long time taking, highly expensive, less percentage of securing, not widely used, chance of hacking and destroy or altered easily. Due to this dearth the present security system is unable to fulfil our best security. In this paper we propose a wireless fingerprint security system based on Zigbee technology to overcome above dearth. This system is based on the taking fingerprint of a user with the help of a fingerprint sensor module and matching it with the database details corresponding to the user fingerprint and displays it on the computer screen. This security system has a better percentage of security with respect to other security system available. Apart from this it is fast processing, less expensive, better portability and a little bit chance of hacking, alter and copy of information between source and database.

Database, Fingerprints Sensor Module, Fingerprints Verification, Zigbee Technology.


1.        M. Lourde R, D. Khosla, “Fingerprint Identification in Biometric Security Systems” International Journal of Computer and Electrical Engineering, Vol. 2, No. 5, October, 2010.
2.        G.Sambasiva Rao, C. NagaRaju, L. S. S. Reddy and E. V. Prasad,“A Novel Fingerprints IdentificationSystem Based on the Edge Detection”, International Journal of Computer Science and Network Security.

3.        International Journal of Engineeringand Advanced Technology  (IJEAT). ISSN: 2249 – 8958, Volume-2, Issue 3, February 2013. 201. “Wireless Fingerprint Based College Attendence System using Zigbee Technology”



6.        A. K. Jain, U. Uludag and A. Ross, "Biometric Template Selection: A Case Study in Fingerprints", Proc. 4th Int'l Conf. on Audio- and Video-Based Biometric Person Authentication (AVBPA), pp. 335-342, Guildford, UK, June 9-11, 2003.

7.        L. Hong and A. K. Jain, "Classification of Fingerprint Images", Proc. 11th Scandinavian Conference on Image Analysis, June 7-11, Kangerlussuaq, Greenland, 1999

8.        “Design of Zigbee Transcevier for IEEE 802.15.4 Using MATLAB/SIMULINK”]Prof. Sarat Kumar Patra (Supervisor) Head of Department, Dept. of Electronics & Communication Engg. National Institute of Technology Rourkela-769008.


10.     R. Cappelli, D. Maio, and D. Maltoni, “Synthetic Fingerprint-DatabaseGeneration,” in Proc. 16th International Conf. on Pattern Recognition,August 2002, pp. 744–747.


12.     Nandakumar K, Jain AK, Pankanti S. Fingerprint-baseFuzzy Vault: Implementation and Performance, IEEE Transactions on InformaticsForensics and Security, vol. 2, no. 4, pp. 744-757, December 2007.




Ajay Singh Yadav, Anupam Swami

Paper Title:

A Two-Warehouse Inventory Model for Decaying Items with Exponential Demand and Variable Holding Cost

Abstract: This chapter presents a two warehouses inventory model for deteriorating items. It is assumed that the inventory costs (including holding cost and deterioration cost) in RW are higher than those in OW. Demand is taken exponentially increasing with time. Holding cost is taken as variable and it is linear increasing function of time. Shortages are allowed in the owned warehouse and the backlogging rate of unsatisfied demand is assumed to be a decreasing function of the waiting time. Profit maximization technique is used in this study.



1.        Aggarwal, S.P. and Jaggi, C.K. (1995): “Ordering policies of deteriorating items under permissible delay in payments”, Journal of Operational Research Society (J.O.R.S.), 46, 658-662.
2.        Balkhi, Z.T. and Benkherouf, L. (2004): “On an inventory model for deteriorating items with stock dependent and time varying demand rates”, Computers & Operations Research, 31, 223- 240.

3.        Dave, U. (1989): “On a heuristic inventory-replenishment rule for items with a linearly increasing demand incorporating shortages. Journal of the Operational Research Society, 38(5), 459-463.

4.        Donaldson W.A. (1977): “Inventory replenishment policy for a linear trend in demand-an analytical solution”. Operational Research Quarterly, 28,663-670.

5.        Goswami, A. and Chaudhuri, K.S. (1991): “An EOQ model for deteriorating items with a linear trend in demand”, J.O.R.S., 42(12), 1105-1110.

6.        Hariga. M.A. (1995): “Effects of inflation and time-value of money on   an inventory model on an inventory model with time-dependent demand rate and shortages”, E.J.O.R., 81 (3), 512-520.

7.        Mandal, M. and Maiti, M. (1999): “Inventory of damageable items with variable replenishment rate, stock-dependent demand and some units in hand”, Applied Mathematical Modeling 23 (1999), pp. 799–807.

8.        Mahapatra, N.K. and Maiti, M. (2005): “Multi objective inventory models of multi items with quality and stock dependent demand and stochastic deterioration”, Advanced Modeling and optimization, 7, 1, 69-84.

9.        Panda, S., Saha, S. and Basu, M. (2007): “An EOQ model with generalized ramp-type demand and Weibull distribution deterioration”, Asia Pacific Journal of Operational Research, 24(1),1-17.

10.     Sana, S., and Chaudhuri, K.S. (2008): “A deterministic EOQ model with delays in payments and price-discounts offer”, E.J.O.R., 184, 509-533.

11.     Wu, K.S., Ouyang, L.Y. and Yang, C.T. (2006): “An optimal replenishment policy for non-instantaneous deteriorating items with stock dependent demand and partial backlogging”, I.J.P.E., 101, 369-384.




Shivani Chauhan

Paper Title:

A Study Single Electron Transistor In Neural Network, Nanotechnology and Memory Design

Abstract: To avail the practical approach for low dimension designing of electronic chips, SET is being used on the highest concern to provide nanotechnology. Now in current days, artificial neural networks is playing important roll for the accuracy and less time response. A computer memory which is basically based on this property would be ability to retain information in case if processor it self powered off. SET  is to be considered as elements for future low power , high density integrated  circuits reason for this of their the potential to involving only few electrons for ultra low power . In this paper we express the study of single electron transistor being used in nanotechnology, artificial neural network & memory designing. The operation as single electron transistor with it’s history is mentioned included with advantages and disadvantage of SET.

Operation of set, Nanotechnology, Neural Network & Current Standards.


1.        M.A. Kastner, “The single Electron Transistor”, Reviews of Modern Physics, Vol. 64, No. 3, pp. 849-858, July 1992.
2.        M. A. Kastner, “The single electron transistor and artificial atoms”, Ann. Phy.  (Leipzig), vol. 9, pp. 885-895, 2000.

3.        S. Bednarek, B. Szafran, and J. Adamowski, “Solution of the Poisson-Schrodinger problem for a single-electron transistor”, Phys. Rev. B, Vol. 61, pp. 4461-4464, 2000.

4.        Songphol Kanjanachuchai and Somsak Panyakeow, “Beyond CMOS: Single-Electron Transistors”, IEEE International Conference on Industrial Technology, Bangkok, Thailand, 2002.

5.        Masumi Saitoh, Hidehiro Harata1ion and Toshiro Hiramoto, “Room-Temperature Demonstration of Integrated Silicon Single-Electron Transistor Circuits for Current Switching and Analog Pattern Matching”, IEEE International Electron Device Meeting, San Francisco, USA, 2004.

6.        K. Matsumoto, M. Ishii, K. Segawa, Y. Oka B. J. Vartanian and J. S. Harris, “Room temperature operation of a single electron transistor made by the scanning tunneling microscope nano oxidation process for the TiOx/Ti system”, Appl. Phys. Lett. 68 (1), pp. 34-36, 1996.

7.        Xiaohui Wang and Wolfgang Porod, “Analytic I-V Modeling for Single-Electron Transistor”, VLSI Design, Volume 13, pp. 189-192, 2001.

8.        J.M. Martinez-Duart, R.J. Martin-Palma, F. Agullo-Rueda, “Nanotechnology for Microelectronics and Optoelectronics”, First Edition, pp.65-169, 2006.

9.        William a. Goddard, Donald W. Brenner, Sergey e. Lyshevski, Gerald J. Lafrate, “Handbook of Nanoscience Engineering and Technology”, Second edition,  pp.13-1 to 13-38, 2007.

10.     Uda Hashim and Amiza Rasmi “Single- Electron Transistor (SET) Process and Device Simulation Using SYSNOPSYS TCAD Tools” American Journal of Applied Sciences 3 (7): 1933-1938, 2006

11.     T.A. Fulton and G.D. Dolan, “Observation of single-electron charging effect in small tunneling junction,” Phys. Rev. Lett., vol.59, pp. 109-112, July 1987.

12.     Dae Hwan Kim, Jong Duk Lee and Byung-Gook Park “Room Temperature Coulomb Oscillation of a Single Electron Switch with an Electrically Formed Quantum Dot and Its Modeling”, Jpn. J. Appl. Phys. Vol. 39 (2000) pp. 2329-2333, April 2000.

13.     Dinh Sy Hien, Huynh Lam Thu Thao and Le Hoang Minh, “Modelling transport in single electron transistor”, APCTP–ASEAN Workshop on Advanced Materials Science and Nanotechnology (AMSN08), Journal of Physics: Conference Series 187,pp. 1-5, 2009.

14.     David Berman, Nikolai B. Zhitenev, Raymond C. Ashoori, Henry I. Smitha and Michael R. Melloch, “Single-electron transistor as a charge sensor for semiconductor applications”, J. Vac. Sci. Technol. B 15(6), pp. 2844-2847, Nov/Dec 1997.

15.     M. N. Kiselev, K. Kikoin, R. I. Shekhter and V. M. Vinokur, “Kondo shuttling in a nanoelectromechanical single-electron transistor”, PHYSICAL REVIEW B 74, 233403, pp. 1-4, 2006.

16.     Lingjie Guo, Effendi Leobandung and Stephen Y. Chou, “A Silicon Single-Electron Transistor Memory Operating at Room Temperature”, SCIENCE VOL. 275, pp. 649-651, 1997.

17.     Dong Seup Lee, Sangwoo Kang, Kwon-Chil Kang, Joung-Eob Lee, Jung Hoon Lee, Kwan-Jae Song, Dong Myong Kim, Jong Duk Lee and Byung-Gook Park, “Fabrication and Characteristics of Self-Aligned Dual-Gate Single-Electron Transistors”, IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 8, NO. 4, pp. 492-497, JULY 2009.

18.     Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert P. Dick and Robert G. Knobel, “Towards An Ultra-Low-Power Architecture Using Single-Electron Tunneling Transistors”, Annual ACM IEEE Design Automation Conference, pp. 312-317, 2007.

19.     Teruhisa Matsui, Jun Kawarabayashi, Kenichi Watanabe and Tetsuo Iguchi, “Evaluation of Single-Electron Transistor as Nanoscale Thermometer for a Cryogenic Radiation Detector”, Journal of NUCLEAR SCIENCE and TECHNOLOGY, Supplement 6, pp. 73–77 September 2008.

20.     R. Knobel, C. S. Yung, and A. N. Clelanda, “Single-electron transistor as a radio-frequency mixer”, APPLIED PHYSICS LETTERS, VOLUME 81, NUMBER 3, pp. 532-534, July 2002.

21.     A.N. Cleand, D. Estene, C. Urbina and M.H. Devoret, “An  Exterimly Low Noise Photodetector

22.     Om kumar and Manjit kaur, “Single electron transistor:  Applications & problems”, International journal of VLSI design and communication system (VLSICS) Vol. 1, No. 4, Dec. 2010.




Sheetal Dixit, Ramanand Harijan

Paper Title:

Design & Analysis of Low Power Low Voltage Regulated Cascode Current Mirror

Abstract: The current mirror is core structure of all most all analog and mixed mode circuits and the performance of analog structures largely depends on their characteristics. In this paper first we study the simple current mirror; cascode current mirror and different low voltage current mirror topology and study the literature survey advantage and disadvantage.  Second we study, analysis and design of convention regulated cascode current mirror, regulated cascade current mirror, wide output swing regulated cascade current mirror and wide input output swing regulated cascode current mirror and simulate Tanner EDA tool T-SPICE 0.18μm CMOS technology. Presented analysis low voltage current mirror input characteristic, output characteristics high output swing capability and wide input and wide output swing capabilities, suitable for low voltage operation and minimum power dissipation.

Low voltage current mirror, level shifted current mirror, cascode current mirror, WIOS –RCCM.


1.        Lopez-Martin,A.J.; Ramirez-Angulo,j.; Carvajal,R.G.,‘‘Low-voltage highly-linear class AB Current mirror with dynamic cascode biasing”IEEE Journal &Magazines, volume 48, Issue:21, ,October 11 2012.
2.        Minch,B.A.,“A simple low voltage cascade Current mirror with enhanced dynamic performance” IEEE conference, PP. no 1-3,9-10 Oct.2012

3.        Garcia-Lozano,R.Z.;Hidalgo-Cortes,C.;Rocha-Perez,J.M.;Diaz-Sanchez,A.,“A very compact CMOS class AB current mirror for low voltage application” IEEE conference on Circuits and systems(CWCAS),, Nov. 2012.

4.        Behzad Razabi,, “Design of analog CMOS integrated circuits”, Tata McGraw Hills, fourth edition, 2001.

5.        S.S Rajput, “Advanced Current Mirror for Low Voltage Analog Designs”, IEEE, ICSE, Proc, vol. 148, pp. 258-263, 2004.

6.        Ying-Chuan Liu, Hung-Yu Wang, Yuan-Long Jeang and Yu-Wei Huang, “A CMOS Current Mirror with Enhanced Input Dynamic Range”, 3rd International Conference on Innovative Computing Information and Control (ICICIC'08).

7.        S.S. Rajput, Prateek Vajpayee, G.K. Sharma, “1V High Performance Current Mirror for Low Voltage Analog and Mixed Signal Applications in Submicron Regime”, IEEE TENCON Conference , pp no.1-4,2009.

8.        Jasdeep Kaur, Nupur Prakash and S.S.Rajput, “High-Linearity Low-Voltage Self- Cascode Class AB CMOS Current Output Stage”, World Academy of Science , Engineering and Technology 41 journal, Electron, pp. 600-6003, 2008.

9.        Timir Datta, Pamela Abshire “Mismatch Compensation of CMOS Current Mirrors Using Floating-Gate Transistors”, solid –state circuits, IEEE Journal ,vol. 25no 3,pp. 1823-1826,2009.

10.     Bruun E and Shah P, “Dynamic range of low-voltage cascode current mirrors”, Proc Circuit and system IEEE Journals, pp.1328-1331,1995.

11.     E. Sackinger, W. Guggenbuhl, “A High-Swing, High-Impedance MOS Cascode Circuit”, IEEE Journal of Solid-state circuits, Vol.25, No.1, pp.289-298, Feb. 1990.

12.     S.S.Rajput  and  S.S.Jamuar, “Low voltage, low power, high performance current mirror for portable analogue and mixed mode applications”, IEEE  Proc-Circuits Device system,Vol. 148,No 5, pp.273-278,2001.

13.     S.S. Rajput and S.S. Jamuar, “Low Voltage Analog Circuit Design Techniques,” IEEE Circuits and Systems Magazine, Vol. 2, Issue: 1, pp.24-42, Jan-Mar 2002.

14.     Klass Bult and G.J.G.M. Geelen, “The CMOS Gain-Boosting Technique,” Analog Integrated Circuits and Signal Processing,Vol.1, Issue 2, pp. 119-135, Oct. 1991.